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CA3260, CA3260A
Data Sheet February 7, 2006 FN1266.6
4MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output
CA3260A and CA3260 are integrated circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA3260 series circuits are dual versions of the popular CA3160 series. Gate protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. A complementary symmetry MOS (CMOS) transistor pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA3260 Series circuits operate at supply voltages ranging from 4V to 16V, or 2V to 8V when using split supplies. The CA3260A offers superior input characteristics over those of the CA3260.
Features
* MOSFET Input Stage provides - Very High ZI = 1.5T (1.5 x 1012) (Typ) - Very Low II . . . . . . . . . . . . 5pA (Typ) at 15V Operation . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation * Ideal for Single Supply Applications * Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail * CMOS Output Stage Permits Signal Swing to Either (Or Both) Supply Rails * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Ground Referenced Single Supply Amplifiers * Fast Sample-Hold Amplifiers * Long Duration Timers/Monostables * Ideal Interface with Digital CMOS * High Input Impedance Wideband Amplifiers * Voltage Followers (e.g. Follower for Single Supply D/A Converter)
Ordering Information
PART NUMBER CA3260E CA3260EZ (Note) CA3260AE PART MARKING CA3260E CA3260EZ CA3260AE TEMP. RANGE (C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld PDIP 8 Ld PDIP* (Pb-free) PKG. DWG. # E8.3 E8.3 E8.3 E8.3
* Voltage Regulators (Permits Control of Output Voltage Down to 0V) * Wien Bridge Oscillators * Voltage Controlled Oscillators * Photo Diode Sensor Amplifiers
CA3260AEZ 3260AEZ (Note)
Pinout
CA3260, CA3260A (PDIP) TOP VIEW
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
OUTPUT (A) INV. INPUT (A) NON INV. INPUT (A) V-
1 A 2 3 4
8 7 B + 6 5
V+ OUTPUT (B) INV. INPUT (B) NON INV. INPUT (B)
-
+
-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
CA3260, CA3260A
Absolute Maximum Ratings
DC Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . 16V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 2) JA (C/W) JC (C/W) PDIP Package* . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Input Resistance Input Capacitance Unity Gain Crossover Frequency Slew Rate Transient Response
TA = 25C, Typical Values Intended Only for Design Guidance TYPICAL VALUES SYMBOL RI CI fT SR Rise Time Overshoot tr OS tS VIO IIO II CMRR AOL TEST CONDITIONS VS = 7.5V f = 1MHz, VS = 7.5V VS = 7.5V VS = 7.5V CL = 25pF, RL = 2k, AV = +1, VS = 7.5V CL = 25pF, RL = 2k, AV = +1, VS = 7.5V V+ = 5V, V- = 0V V+ = 5V, V- = 0V V+ = 5V, V- = 0V V+ = 5V, V- = 0V VO = 4VP-P, RL = 20k, V+ = 5V, V- = 0V V+ = 5V, V- = 0V VO = 5V, RL = , V+ = 5V, V- = 0V VO = 2.5V, RL = , V+ = 5V, V- = 0V VIO/V+, V+ = 5V, V- = 0V CA3260A 1.5 4.3 4 10 0.09 10 1.8 2 0.1 2 70 100 100 0 to 2.5 1 1.2 200 CA3260 1.5 4.3 4 10 0.09 10 1.8 6 0.1 2 60 100 100 0 to 2.5 1 1.2 200 UNITS T pF MHz V/s s % s mV pA pA dB kV/V dB V mA mA V/V
Settling Time (to <0.1%, VIN = 4VP-P) Input Offset Voltage Input Offset Current Input Current Common Mode Rejection Ratio Large Signal Voltage Gain
Common Mode Input Voltage Range Supply Current
VICR I+
Power Supply Rejection Ratio
PSRR
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Large Signal Voltage Gain
For Each Amplifier at TA = 25C, V+ = 15V, V- = 0V, Unless Otherwise Specified TEST CONDITIONS VS = 7.5V VS = 7.5V VS = 7.5V VO = 10VP-P, RL = 10k CA3260A MIN 50 94 80 0 TYP 2 0.5 5 320 110 95 -0.5 to 12 MAX 5 20 30 10 MIN 50 94 70 0 CA3260 TYP 6 0.5 5 320 110 90 -0.5 to 12 MAX 15 30 50 10 UNITS mV pA pA kV/V dB dB V
SYMBOL |VIO| |IIO| II AOL
Common Mode Rejection Ratio Common Mode Input Voltage Range
CMRR VlCR
2
FN1266.6 February 7, 2006
CA3260, CA3260A
Electrical Specifications
PARAMETER Power Supply Rejection Ratio Maximum Output Voltage For Each Amplifier at TA = 25C, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued) TEST CONDITIONS VIO/V+ V+ = 17.5V RL = 10k RL = CA3260A MIN 11 14.99 VO = 7.5V 12 12 RL = VIO/T f = 1kHz 9 1.2 5 6 120 15.5 3 8.5 9 1.2 5 8 120 15.5 3 8.5 mA mA mA V/C dB TYP 32 13.3 0.002 15 0 22 20 MAX 150 0.01 0.01 45 45 MIN 11 14.99 12 12 CA3260 TYP 32 13.3 0.002 15 0 22 20 MAX 320 0.01 0.01 45 45 UNITS V/V V V V V mA mA
SYMBOL PSRR VOM+ VOMVOM+ VOM-
Maximum Output Current
IOM+ Source IOM- Sink
Total Supply Current VO (Amplifier A) = 7.5V VO (Amplifier B) = 7.5V VO (Amplifier A) = 0V VO (Amplifier B) = 0V VO (Amplifier A) = 0V VO (Amplifier B) = 7.5V Input Offset Voltage Temperature Drift Crosstalk
I+
Schematic Diagram
8 V+ AMPLIFIER A AMPLIFIER B
Q11
Q10 D2
Q6
Q7 Q9 D3 Q23
Q21
Q20 Q24
Q25 D7
D6
D1 Q12 Q14 Q13 R3 1K Q3 R1 1K 3 Q1 Q2
D4
R5 2K C1 30pF Q5 Q8 Q22
R12 2K C2 30pF Q19
D5 Q16 Q15 R11 1K
D8
Q26 R10 Q27 1K Q17 R14 300 Q28
R4 1K
R6 200K
R7 300K
Q4 R2 1K 2 1 7 6
Q18 R9 1K R8 1K
R13 200K
5
4
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 3
FN1266.6 February 7, 2006

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